1. Field of the Invention
The present invention relates to a method and apparatus for managing multiple out-of-order packetized data streams in a network or computer system.
2. Background Information
One of the standard bus architectures found in personal computers and workstations is the Peripheral Component Interconnect (PCI) bus. A PCI bus is comprised of a set of wires that electronically interconnect various semiconductor chips and input/output devices of a computer system. Electronic signals are transmitted over the bus so that various components can communicate with each other. A PCI host bridge is a device that buffers data and translates transaction format between an industry standard PCI bus and a proprietary expander bus in most modern workstations and server platforms. The system bus and PCI bus are not physically connected, however, the PCI bridge establishes a xe2x80x9cbridgexe2x80x9d between the two buses to allow data transfers between them.
PCI delayed read requests can be represented internally to a chipset as split transactions composed of a request packet containing header information and a completion packet containing identification information and, in general, a portion of the requested read data. For a host bridge that made a request to match the returning completion packet with the proper request packet, lengthy decoding either by full source or destination address field decoding or other methods are typically required. The matching of request and completion packets adds to transaction process latency. Once the completion is matched to the request, the bridge will then buffer the data until the requesting PCI master queries the PCI host bridge. That is, the PCI master is required to poll the target of the delayed request until at least one data transfer is consumed. Therefore, the PCI master must receive one unit of data transfer from the completion packet stream before it is allowed to retire its request. This is known as read retrying. When the requesting PCI master returns, the bridge begins transferring the data belonging to the requesting master, sometimes stitching multiple expander bus packets together to provide continuous data streaming onto the PCI bus. Both the PCI host bridge and PCI master are capable of using linear address bursting as described in PCI Local Bus Specification, Revision 2.1 and 2.2, by the PCI Special Interest Group, Portland, Oreg.
Data requested by a particular PCI master, starting at a particular address, and requested in an ordered contiguous address range (starting at the lowest address and incrementing) will be referred to as a data stream. Since most PCI buses support multiple PCI masters, a high performance host bridge will need to generally have the capability to handle more than one data stream at any given point in time. Additionally, to provide high throughput read data delivery, the host bridge will generally be required to hide a large portion of the chipset latency by maintaining multiple request packets outstanding to the expander bus interface at any given instant.
Due to the nature of the chipset I/O and memory subsystem designs, the read completion packets associated with a particular data stream may be returned to the host bridge out of sequential order. Current PCI host bridge designs do not provide the capability for efficiently managing multiple out-of-order packetized data streams where multiple packets (per stream or for a set of streams) may be outstanding to chipset components. The host bridge is responsible for reassembling each PCI data stream as packets are returned by the expander bus interface. Reassembly includes properly ordering the packets into one xe2x80x9cstitchedxe2x80x9d sequential data stream and identifying which returning packets belong to what PCI data streams. An additional problem is that a PCI master may stop reading a particular read stream and begin a new one at any point after consuming the first data transfer of an existing stream. Therefore, a high performance host bridge must be capable of changing the stream context and issuing new stream packets prior to the previously sent packets returning from the expander bus interface. Buffer space is limited, therefore, the host bridge will generally reuse the previously allocated stream buffer.